USART in Atmel AVR (ATMEGA88 and ATMEGA328P)
The main features of the USART module in the AVR micro controller are:
1.Full Duplex Operation with Independent Serial Receive and Transmit Registers
2.Asynchronous or Synchronous Operation
3.Master or Slave Clocked Synchronous Operation
4.High Resolution Baud Rate Generator
5.Data OverRun Detection
6.Framing Error Detection
7.Supports Serial Frames with 5, 6, 7, 8, or 9 Data bits and 1 or 2 Stop Bits
8.Odd or Even Parity Generation and Parity Check Supported by Hardware
9.Multi-processor Communication Mode
10.Double Speed Asynchronous Communication Mode
11.Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
12.Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
13.Multi-processor Communication Mode
14.Double Speed Asynchronous Communication Mode
The USART is built around three modules: Clock Generator, Transmitter and Receiver.
Note: the control registers are shared by all the modules.
The following paragraphs describes how to use the USART in Atmega328P and Atmega88.
Clock Generation logic
The Clock Generation logic consists of synchronization logic for external clock input (XCKn pin, the transfer clock pin) used by synchronous slave operation, and by the baud rate generator used in synchronous and asynchronous operations. It gives the clock for the receiver and the transmitter. The USART supports four modes of clock operations :Normal Asynchronous
Double Speed Asynchronous
Master Synchronous
Slave Synchronous
Serial mode selection.
The serial mode (synchronous/asynchronous) is selected by the UMSEL0 bit in the UCSR0C register. The double speed (only asynchronous) is controlled by the U2X0 of the UCSR0A register. In synchronous operations, the data direction register for the XCK0 pin controls if the clock source is internal (Master mode) or external (Slave Mode).
Internal clock generation.
The internal clock generation is used in asynchronous and synchronous master mode operations. The setting up of the baud rate is performed using the USART Baud Rate Register (UBRR0) and the down-counter prescaler. The down-counter, running at system clock (fosc), is loaded with the UBRR0 value each time the counter has counted down to zero or when the UBRR0L Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR0+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units.
The expressions used to compute the baud rate are described in following figure (Atmega328p User manual) according to the proper mode of operations.
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Operating Mode
Equation for Calculating Baud Rate
Equation for Calculating UBRRn Value
Asynchronous Normal Mode (U2*n=0)
Asynchronous Double Speed Mode (U2*n=1)
Synchronous Master Mode
In double speed operation the transfer rate could be doubled setting the U2X0 bit. This bit reduce the divisor of the baud rate generator from 16 to 8, but the receiver will use only half number of the samples for data sampling and clock recovery, so a more accurate system clock is required.
In synchronous master mode operation the clock is output by the XCK0 pin.
External clock
The external clock is only used by the synchronous slave mode operation. The external clock inputs from the XCK0 pin and the maximum clock frequency is limited to the quarter part of fosc (fosc/4).
(to be continued…)