The USART Transmitter is enabled setting the Transmit Enable (TXEN) bit in the UCSR0B Register. When the Transmitter is enabled, the normal port operation of the TxD0 pin is overridden by the USART and given the function as the Transmitter’s serial output.
The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
If synchronous operation is used, the clock on the XCK0 pin will be overridden and used as transmission clock.
A data transmission is initiated by loading the transmit buffer (UDR0 I/O location) with the data to be transmitted.
The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register, U2X0 bit or by XCK0 depending on mode of operation.
The USART Transmitter has two flags that indicate its state: Data Register Empty (UDRE0) and Transmit Complete (TXC0).
The Data Register Empty (UDRE0) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register.
The USART gives also the possibility to generate interrupts during the transmission. Two types of interrupt can be defined : the Data Register Empty Interrupt and the Transmit Compete Interrupt.
The USART can generate interrupt if the data register is empty and for this purpose it has one bit that enable/disable the Data Register Empty Interrupt generation: the Data Register Empty Interrupt Enable(UDRIE0) .
When the UDRIE0 bit in UCSR0B is written to one, the USART Data Register Empty Interrupt will be executed as long as UDRE0 is set (if the global interrupts are enabled).
The UDRE0 flag is cleared by writing UDR0.
When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDR0 in order to clear UDRE0 or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates.
The USART can also generate an interrupt when a the transmission is complete (Transmit Complete Interrupt).
The Transmit Complete (TXC0) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC0 Flag is useful in half-duplex communication interfaces where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIE0) bit in UCSR0B is set, the USART Transmit Complete Interrupt will be executed when the TXC0 Flag becomes set (if global interrupts are enabled). When the transmit complete interrupt is used, the interrupt handling routine does not have to clear the TXC0 Flag, this is done automatically when the interrupt is executed.
The transmitter can be disabled setting the TXEN bit to zero in the UCSR0B register.
The USART Receiver is enabled writing the Receive Enable (RXEN0) bit in the UCSR0B register to one.
When the Receiver is enabled, the normal pin operation of the RxD0 pin is overridden by the USART and given the function as the Receiver’s serial input.
The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK0 pin will be used as transfer clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK0 clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR0 I/O location.
The USART Receiver has the Receive Complete (RXC0) Flag that indicates if there are unread data present in the receive buffer.
This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
If the Receiver is disabled (RXEN0 = 0), the receive buffer will be flushed and consequently the RXC0 bit will become zero.
The USART can generate interrupt when the RXC0 flag is set and for this purpose it has one bit that enable/disable the Receive Complete Interrupt generation: the Receive Complete Interrupt Enable (RXCIE0) .
When the Receive Complete Interrupt Enable (RXCIE0) in UCSR0B is set, the USART Receive Complete interrupt will be executed as long as the RXC0 Flag is set (if global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR0 in order to clear the RXC0 Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
(to be continued…)